1. Field of the Invention
The present invention relates to a time measurement technique.
2. Description of the Related Art
Time to digital converters (which will be referred to as “TDCs” hereafter) are known that are configured to convert the time difference in transition timing between a first signal (which will be referred to as the “start signal” hereafter) and a second signal (the “stop signal”) into a digital value. A method employing a vernier delay circuit has been proposed as a TDC having high time resolution.
FIG. 1 is a diagram which shows a configuration of a TDC 300 employing a vernier delay circuit 200. The TDC 300 includes the vernier delay circuit 200 and a priority encoder 100. The vernier delay circuit 200 receives a start signal Sstart and a stop signal Sstop, and generates a thermometer code TC in which the bits change at a particular bit position that corresponds to the time difference between these two signals. The vernier delay circuit 200 includes a first delay circuit 210, a second delay circuit 220, and thermometer latches TL0 through TLN.
The first delay circuit 210 includes N multistage connected first delay elements D1. The first delay circuit 210 applies a first predetermined delay amount t1 to the start signal Sstart at every stage, and outputs (N+1) delayed start signals SA0 through SAN to which different respective delay amounts are applied. In the same way, the second delay circuit 220 includes N multistage connected second delay elements D2. The second delay circuit 220 applies a second predetermined delay amount to the stop signal Sstop at every stage, and outputs (N+1) delayed stop signals SB0 through SBN to which different respective delay amounts are applied.
The first predetermined delay amount t1 is set to be longer than the second predetermined delay amount t2. The relative time difference between the start signal Sstart and the stop signal Sstop is reduced by Δt=(t1−t2) every time the start signal Sstart and the stop signal Sstop respectively pass through a delay element stage of the first delay circuit 210 and the second delay circuit 220. In a case in which the initial time difference between the start signal Sstart and the stop signal Sstop is π, the edge timing relation between these two signals reverses at a stage in which the start signal Sstart and the stop signal Sstop have each passed through (π/Δt) delay element stages.
The j-th (j represents an integer which satisfies the relation 0≦j≦N) thermometer latch TLj latches the delayed stop signal SBj output from the j-th stage delay element at a timing of the delayed start signal SAj output from the j-th stage delay element. In the present specification, the stage immediately before the first stage will be referred to as the “0-th stage” for convenience. That is to say, the 0-th thermometer latch TL0 receives the start signal before any delay is applied and the stop signal before any delay is applied.
As a result, until the stage in which the stop signal Sstop catches up with the start signal Sstart, the corresponding thermometer latches TL each output an output signal of 0. After the stage in which the stop signal Sstop overtakes the start signal Sstart, the corresponding thermometer latches TL each output an output signal of 1. Thus, the data latched by the (N+1) thermometer latches TL0 through TLN is output as a thermometer code TC[0:N]. The term “thermometer code” is thus named because it operates in a manner similar to a thermometer, in that the value of the thermometer code is switched from 1 to 0 (or 0 to 1) with a particular bit as a boundary.
It should be noted that, in a case in which the stop signal Sstop cannot catch up with the start signal Sstart, all the bits of the thermometer code TC are set to 0, and in a case in which the stop signal Sstop is input before the start signal Sstart, all the bits of the thermometer code TC are set to 1.